At Siemens EDA, I work on Questa simulation issues, investigating SystemVerilog semantics, concurrency, and scheduling. I own high-severity correctness and performance bugs and serve as an escalation point for difficult issues.
Earlier at Siemens EDA, I improved functional coverage workflows, reducing the time to reach target coverage from weeks to hours. As a student intern, I integrated Boolector into Questa Sim and implemented incremental and assumption-based solving.
