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Vidyasagar Belkatte

@vidyasagarbelkatte

Aspiring Physical Design Engineer trained in the RTL-to-GDSII flow; worked on a full-chip ASIC design using TSMC 65nm technology.

India

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What I'm looking for

I'm seeking an entry-level position in Physical Design, STA, or Front-End Design where I can contribute to semiconductor development.

During my VLSI training at ChipXpert, I worked on a full-chip ASIC design using TSMC 65nm, 9-layer technology. I performed the RTL-to-GDSII flow from synthesis to post-route timing analysis using Cadence Genus, Innovus, and Tempus.

I also developed TCL scripts to automate repetitive EDA tasks and wrote basic Verilog modules for combinational and sequential circuits. In my Contactless Door Control project, I developed C++ code for sensor-triggered door operation using a state machine.

Experience

Work history, roles, and key accomplishments

Current

VLSI Design & Physical Design Engineer (Aspiring)

Current

ChipXpert

Jan 2026 - Present (9 months)

Undergoing intensive VLSI training covering the full Physical Design flow from RTL to GDSII, including CMOS design, digital design, Verilog, synthesis, STA, LEC, DTA, TCL, and physical design.

Verilog Synthesis STA LEC DTA Tcl Physical Design Linux CMOS Circuit Design Digital Electronics

Education

Degrees, certifications, and relevant coursework

ChipXpert

VLSI Design & Physical Design Course, VLSI Design and Physical Design

2026 -

Activities and societies: Hands-on practice with Linux-based EDA tool environments.

Ongoing 9-month intensive training in VLSI design flow covering 20+ modules, including CMOS design, digital design, Verilog, synthesis, STA, LEC, DTA, TCL, and physical design.

BMS Institute of Technology and Management

Bachelor of Engineering, Electronics and Telecommunication

Grade: CGPA: 7.59

Bachelor of Engineering in Electronics and Telecommunication with a CGPA of 7.59. Relevant coursework includes microprocessors, embedded systems, digital electronics, computer architecture, and VLSI design.