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Nameer Iqbal Ansari

@nameeriqbalansari

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Digital Design Engineer specializing in SoC architecture and RTL development.

Pakistan

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What I'm looking for

I seek a challenging role in a dynamic environment that fosters innovation and growth, where I can leverage my skills in digital design and contribute to cutting-edge projects.

I’m Nameer Iqbal Ansari, a Computer Systems Engineer with a robust background in digital design and SoC architecture. My experience encompasses RTL development using HDLs like SystemVerilog and Verilog, as well as FPGA-based prototyping. I have worked extensively on cache coherence microarchitecture and multi-core memory hierarchies, integrating interconnect protocols such as AXI and TileLink, and utilizing debug hardware like JTAG and logic analyzers.

At XCLR Technologies, I designed and verified various digital circuit components, including complex cache memories and load-store units. I conducted extensive simulation and emulation testing, ensuring high performance and reliability in SoC designs. My role involved creating detailed micro-architecture diagrams and maintaining comprehensive design documentation to facilitate cross-team collaboration. I am passionate about optimizing designs for performance, power, and area (PPA), and I have successfully integrated high-speed Chip-to-Chip SerDes communication IP.

Experience

Work history, roles, and key accomplishments

Current

Associate Engineer

Current

XCLR Technologies (Pvt.) Ltd.

Jan 2025 - Present (7 months)

Designed and verified various digital circuit components, including vector load-store units, matrix multiplication units, multilayered cache memories, and clock/reset generator modules at the RTL level. Conducted PPA analysis and resolved physical design issues in the RTL to evaluate and optimize configurable IP blocks, defined and validated performance goals.

RTL Vivado Questa

Current

Research Assistant

Current

Micro Electronics Research Lab (MERL)

Jan 2020 - Present (5 years 7 months)

Designed, simulated, and emulated an RV32I CPU in SystemVerilog using FuseSoC and Verilator on artya7 FPGA. Guides students and junior engineers on RISC-V open-source architecture, CPU pipeline design, and verification methodologies.

Verilator RISC V CPU Pipeline Design TLUH Bus

Engineer

Xcelerium

Jan 2023 - Present (2 years 7 months)

Designed and validated digital logic for CPU-memory integration and JTAG debug infrastructure at SoC level for FPGA implementations, contributing to embedded system development. Executed hardware debugging using logic analyzers, assisted with hardware rework, and participated in root cause analysis for bring-up issues.

AWS FPGA

Internee

Xcelerium

Jan 2022 - Present (3 years 7 months)

Gained experience in RTL verification and MakeFile scripting. Utilized tools such as VCS, Questa, Verilator, and AWS-FPGA for various projects.

Makefiles VC Questa Verilator AWS FPGA

Education

Degrees, certifications, and relevant coursework

Usman Institute of Technology

Bachelor's Degree, Electrical Engineering (Computer Systems)

2019 - 2023

Grade: 3.28/4

Activities and societies: LIFT scholarship 2024-2025, Google Summer Of Code’23 mentor 2023, Google Summer Of Code’22 contributor 2022, HASHAM CHARITABLE FOUNDATION 2021-2022

Completed a Bachelor's Degree in Electrical Engineering with a focus on Computer Systems. Coursework included Digital Logic Design, Computer Architecture, Microprocessor, and Embedded Systems.