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Zain Saeed

@zainsaeed1

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I build RTL-to-GDSII processors and ASIC implementations for RISC-V and data-intensive hardware systems.

Pakistan

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What I'm looking for

I'm looking to solve complex semiconductor hardware challenges in RTL design, ASIC implementation, physical design, verification, RISC-V systems, and hardware accelerators.

I've built complete RTL-to-GDSII processor implementations and custom RISC-V microarchitectures, including a 3-stage pipelined processor taken through synthesis, floorplanning, placement, routing, DRC, and LVS verification.

For my final-year MegIS project, I replicated and validated an in-storage processing architecture for metagenomic analysis. I implemented SSD-side SystemVerilog RTL, ran synthesis and physical design with Yosys and OpenROAD, and evaluated system-level performance using MQSim.

I'm also a UET Lahore Electrical Engineering student and former Programming Fundamentals Teaching Assistant, with hands-on work in AXI-Lite integration, embedded control systems, hardware debugging, and machine-learning-based sound classification.

Experience

Work history, roles, and key accomplishments

Teaching Assistant

UET Lahore

Sep 2023 - Dec 2023 (3 months)

Assisted undergraduate students in programming fundamentals, laboratory exercises, debugging, and assignment evaluations.

Debugging

Education

Degrees, certifications, and relevant coursework

University of Engineering and Technology (UET), Lahore

Bachelor of Science, Electrical Engineering

Grade: 3.22/4.00

Activities and societies: Relevant Coursework: Digital Logic Design, Electronics Devices and Circuits, Computer Architecture, Microprocessor Systems, VLSI Design, Embedded Systems.

Pursuing a Bachelor of Science in Electrical Engineering with a focus on VLSI design and computer architecture. Achieved a CGPA of 3.22/4.00 through the 7th semester.