At 10xEngineers, I verify the memory subsystem of a superscalar, multicore, out-of-order RISC-V compute chiplet for a U.S.-based client using SystemVerilog and UVM. I debug regressions and drive coverage closure, raising LSU coverage from 86% to 96%.
At CHASE Lab, I designed a compact, low-power spiking neural network for real-time neuronal spike sorting, reaching 97.8% accuracy across simple-spike, complex-spike, and noise classes. I also designed and conducted labs for “VLSI for Artificial Intelligence,” applying Cadence tools to the Netlist-to-layout flow.
At IC Design Lab, I developed a fixed-point SystemVerilog ECG processor for my master’s thesis, with R-peak detection at 99.66% F1 and 99.91% agreement between RTL and a Python model. I also designed RISC-V PLIC and floating-point unit RTL, and verified AXI Lite using Questa Verification IP.
At Re-Engineering with Research (RWR Private Ltd), I developed Verilog RTL and verified SoCs for a baseband transceiver board, including a custom CHDR layer for an SDR. My work also covered JESD204B, AXI4, AHB, APB, and DMA protocols.
