Ahmad Abdullah

I’m a Digital IC design intern currently focused on hardware design, processor architecture, and verification. My training and projects center on turning architecture into working RTL with confidence from simulation-based validation.

At the NUST Chip Design Centre, I completed intensive modules in C Programming, Digital Logic Design, RISC-V Assembly Language, and Computer Architecture. I designed and implemented a 5-stage pipelined single-cycle RISC-V processor (RV32I) with Verilog RTL, integrating core modules like ALU, register file, and hazard detection, then verified functional correctness.

I’ve also contributed to verification, debugging, and optimization by ensuring correct pipeline hazard handling and compliance with the RV32I instruction set. In my projects, I built modular processor datapaths and used Xilinx Vivado with testbenches and waveform analysis to strengthen my control-signal and instruction decoding understanding.

Beyond processors, I implemented a reduced Rijndael (AES) cipher in hardware using SystemVerilog. I designed and simulated SubBytes, ShiftRows, MixColumns, and AddRoundKey, developing modular units for substitution-permutation operations and round key generation while validating results against software-based AES behavior.