Umar Salim

Working as a Design Verification Engineer, specializing in UVM-based verification using SystemVerilog, Cadence Xcelium, QuestaSim, and EDA Playground. Currently verifying a complete DDS core, developing robust testbenches, functional coverage, assertions, and verification environments to ensure reliable RTL functionality.

As an NFV Engineer within the Core Network department, I specialize in the end-to-end delivery and architectural validation of Network Functions Virtualization projects. My role focuses on the deployment and integration of NE virtualization, ensuring that complex network architectures are implemented correctly and operate with peak stability. I am responsible for overseeing the transition from leg

Completed intensive training in full-stack chip design and verification methodologies. Gained hands-on experience across the complete ASIC design flow, from RTL design to physical implementation and verification. Developed proficiency in industry-standard tools and languages including SystemVerilog for verification, Verilog for RTL design, and C++ for testbench development. Worked extensively with

Developed autonomous AI agents for blockchain applications using Rust and Solana blockchain platform. Built intelligent agent systems that operate at the intersection of AI and decentralized technology, enabling automated smart contract interactions and decision-making processes. Contributed to democratizing advanced agentic AI and blockchain solutions for businesses.
Key Technologies: Agentic AI,

Developed AI-based solutions for Safe City initiatives focusing on disaster management, environmental monitoring, and autonomous threat detection. Implemented and optimized deep learning models including CNN, R-CNN, Fast R-CNN, Faster R-CNN, and YOLO for real-time event detection. Utilized Roboflow for dataset management and model deployment, contributing to smart city safety systems that balance