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Sobia ZafarSZ
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Sobia Zafar

@sobiazafar

Senior FPGA engineer at Public Sector Organization who delivered real-time thermal imaging and detection systems.

Pakistan
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At Public Sector Organization, I architect and implement FPGA DSP and digital pipelines for real-time applications, translating MATLAB models into optimized RTL under strict power and latency constraints.

I designed reusable FPGA IP for thermal imaging, including non-uniformity correction, filtering, autofocus, contrast enhancement, and sharpening. On the 2-FOV Forward-Looking Thermal Imager, I designed Virtex-5 pipelines that delivered real-time 25 fps under DO-254-compliant workflows.

My project work also includes an Artix-7 face detection and temperature monitoring system for COVID-19 checkpoints, plus an aerial target detection pipeline that increased detection range by 25% in field trials. I mentor FPGA and verification engineers and work across verification, hardware-in-the-loop testing, and system integration.

Experience

Work history, roles, and key accomplishments

PO
Current

Senior FPGA & Embedded Vision Engineer

Public Sector Organization

Sep 2011 - Present (15 years 1 month)

Architected and implemented DSP and digital pipelines on FPGA for real-time applications, meeting strict power and latency constraints. Translated MATLAB DSP models into optimized RTL implementations and mentored a team of FPGA developers and verification engineers.

Education

Degrees, certifications, and relevant coursework

National University of Sciences and Technology (NUST) logoNN

National University of Sciences and Technology (NUST)

Master of Science, Electrical Engineering

2015 - 2018

Grade: 3.7/4.0

MS in Electrical Engineering with a focus on Digital Signal Processing and Systems. Thesis on hardware implementation of self-adaptive plateau equalization for real-time IR image contrast enhancement.

University of Engineering and Technology Taxila logoUT

University of Engineering and Technology Taxila

Bachelor of Science, Electrical Engineering

2007 - 2011

Grade: 3.68/4.0

BS in Electrical Engineering with a thesis on object following robot.

DO

Doulos

Embedded Systems HW/SW Design, Embedded Systems

Completed training in Embedded Systems Hardware/Software Design.

TH

The Highbrows

Vivado HLS Workshop, FPGA Design

Completed Vivado HLS workshop.

Tech stack

Software and tools used professionally

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