Open to opportunities

KANAN BAJAJ

@kananbajaj1

Message

I build RTL, ASIC, and FPGA systems from Verilog design through implementation.

India

Message

What I'm looking for

I'm looking for opportunities in ASIC design, RTL development, functional verification, or FPGA-based digital system design where I can contribute to hands-on implementation and grow through challenging semiconductor and hardware projects.

At IIT Jodhpur, I reviewed, debugged, and validated an open-source FlashAttention online-softmax accelerator, resolving RTL, synthesis, and algorithmic issues through simulation and iterative debugging.

I executed RTL-to-GDSII implementation with OpenLane and Sky130A, evaluating timing, area, and power across iterations. I also designed a synthesizable Q16.16 fixed-point Softmax accelerator with a pipelined exponential unit, reciprocal-LUT normalization, and FSM-based control.

I'm pursuing Electronics and Communication Engineering while building FPGA, ASIC, embedded, and data-driven projects, including a real-time ECG monitor on Digilent Nexys A7 and a 110 sequence detector through the Synopsys RTL-to-GDSII flow.

Experience

Work history, roles, and key accomplishments

Research Intern

Indian Institute of Technology, Jodhpur

May 2026 - Jul 2026 (2 months)

Completed an 8-week research internship under Dr. Binod Kumar, focusing on RTL design, ASIC implementation, and Softmax hardware accelerator development. Reviewed, debugged, and functionally validated an open-source FlashAttention online-softmax accelerator, and executed the complete RTL-to-GDSII implementation using the OpenLane (Sky130A) flow.

Deep Learning OpenLane ASIC Flow Physical Design RTL Design