At Indian Institute of Technology, Jodhpur, I’m working on circuit and system design approaches for AI hardware acceleration, with a focus on In-Memory Computing and its application in genomics.
I designed and simulated a high-speed Double Tail Latch Comparator in CMOS using Cadence Virtuoso, analyzing offset voltage, propagation delay, and power consumption for mixed-signal applications.
I also designed and implemented the Needleman-Wunsch sequence alignment algorithm in Verilog HDL using Xilinx Vivado, including scoring matrix computation, traceback, and alignment generation for FPGA. Earlier, I worked on wireless charging for long-distance power transfer as a project leader at RJIT.
