Open to opportunities

Ojasvita Singh

@ojasvitasingh

Digital VLSI student optimizing ASIC power with RTL modeling, STA, and fine-grain gating for energy-efficient multipliers.

India

Message

What I'm looking for

I’m aiming to work on energy-efficient ASIC/RTL design—building and verifying low-power digital circuits with RTL-to-gate flows, STA, and switching-activity analysis.

I’m an Electronics Engineering student working on digital VLSI design and low-power semiconductor architectures, with a focus on RTL modeling and power optimization. My research on a Wallace Tree Multiplier used fine-grain signal gating and layer-aware gating to cut total power by 54.23%.

I’ve gone end-to-end through the RTL-to-gate flow with the SkyWater SKY130 PDK, running timing and power analysis using OpenSTA and VCD switching activity. I’ve also built a 64-bit RISC-V pipelined processor in SystemVerilog with hazard detection and forwarding, plus an N-bit ALU supporting 16 operations verified in ModelSim.

Experience

Work history, roles, and key accomplishments

Summer Intern

Banaras Locomotive Works

Jul 2025 - Aug 2025 (1 month)

Participated in research on enhancing efficiency and reliability of locomotive electronic systems. Analyzed technical documentation and gained hands-on exposure to fault diagnostics and signal processing techniques.

Matlab LabVIEW Vivado Signal Processing Technical Documentation