At Wipro Limited, supporting Intel Corporation, I owned end-to-end verification for a PCIe-to-AXI bridge subsystem on the Intel FPGA Host Interface Xeon platform.
I built functional coverage models, integrated Hierarchical Verification Plans, mapped 500+ coverage bins, and wrote targeted SystemVerilog sequences that drove functional coverage to 100%.
I also automated Linux regression runs, triaged PCIe and AXI failures in Verdi and DVE, managed release branches, and mentored junior engineers on regression workflows and waveform analysis.
