At Cadence Design System, I work on physical design projects spanning floor planning, pin planning, and place-and-route. In my current TSMC N5 project, I performed die size estimation and floorplan experiments that achieved 99% MFU.
For the same project, I worked on SOC floor planning and pin planning, chip-top channel G-Route analysis, and repeater placement for timing closure. I also implemented physical cell placement, MV power domains, and a custom clock tree for major chip-top clocks.
On a TSMC N4P 16-lane PCIE sub-system, I worked on hierarchical partitioning, sub-block pin placement, and PnR implementation. I adjusted pin placement and IO constraints to address congestion and interface timing.
Across earlier AMD projects, I worked on feedthrough planning, timing closure, DRV and IREM fixes, and ECO-stage setup and hold fixes. My tools include Innovus, Tempus, ICC2, and Prime Time, and I script with C-shell, Perl, and TCL.
