SUJALA B R
@sujalabr
I'm an analog layout engineer transforming circuit schematics into manufacturable silicon.
IndiaWhat I'm looking for
At Texas Instruments, I developed custom IC layouts in Cadence Virtuoso for digital blocks including logic gates, D flip-flops, and clock generators, as well as analog blocks such as current mirrors, differential amplifiers, and LDOs.
I've performed DRC, LVS, antenna verification, and LDE mitigation while optimizing layouts for matching, symmetry, routing, and parasitic effects. I enjoy working across the custom analog layout flow, participating in design reviews, and learning from experienced layout engineers.
I'm building on hands-on projects in LDO layout implementation, single-stage amplifier design, custom digital circuit layouts in GPDK180, and op-amp calculator design. As President of the IC Design Club at NIE, I also bring leadership and a strong interest in impactful semiconductor innovation.
Experience
Work history, roles, and key accomplishments
Developed custom IC layouts in Cadence Virtuoso following foundry design rules for digital and analog blocks. Performed DRC, LVS, antenna verification, and LDE mitigation, optimizing layouts for matching, symmetry, routing, and parasitic effects.
Education
Degrees, certifications, and relevant coursework
The National Institute of Engineering, Mysuru
Bachelor of Engineering, Electronics and Communication Engineering
2022 -
Grade: 8.84
Activities and societies: President of IC design club at NIE (2024-2025); Educational Lead and Volunteer at NGO Youth for Seva.
Pursuing a Bachelor's degree in Engineering with a focus on analog layout design and VLSI. Achieved a GPA of 8.84.
Availability
Location
IndiaAuthorized to work in
Job categories
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