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@autovlogsuser

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I build full-custom analog IC layouts for CMOS and BCD technologies using Cadence Virtuoso.

India

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What I'm looking for

I'm looking for an analog IC layout role where I can contribute to full-custom CMOS and BCD layouts, physical verification, and tape-out work while growing my VLSI design experience.

I've worked at STMicroelectronics on full-custom analog IC layout development for CMOS and BCD technologies, including BCD90nm and BCD45nm designs. My work covers floorplanning, device placement, routing, schematic-to-layout correlation, and physical verification through tape-out.

I've designed charge pump, MOM capacitor, ESD protection, Op-Amp, resistor ladder, ADC-DAC, bandgap reference, and LDO layouts. I use Cadence Virtuoso, Maestro, Modgen, and Siemens Calibre to debug DRC, LVS, ERC, and DFM issues and improve layout area efficiency.

Experience

Work history, roles, and key accomplishments

Analog Layout Intern

ST Microelectronics

Jul 2025 - Jun 2026 (11 months)

Worked on full-custom analog IC layout development using Cadence Virtuoso, including hierarchical layouts and schematic-to-layout correlation. Debugged DRC, LVS, and DFM violations to ensure successful tape-out.

Maestro Siemens Calibre DRC LVS DFM Routing Physical Verification

Analog Layout Design Intern

STMicroelectronics

Jul 2025 - Jun 2026 (11 months)

Completed full-custom layout flow including floorplanning, placement, routing, and DRC/LVS/ERC/DFM verification. Designed area-efficient MOM capacitor layout and charge pump block for non-volatile memory.

Floor Plan Design Placements Routing DRC LVS DFM Charge Pump Bandgap Reference