Abhijit Kumar Manna User

I’m a VLSI engineer with 8 months of experience in full-custom analog layout and CMOS circuit design. I’ve worked on a MeitY-funded mixed-signal processor design project, focusing on stability and performance trade-offs. My hands-on work covers current mirrors, amplifiers, and OTA-C circuits with parasitic-aware layout.

In my Project Associate role at West Bengal University of Technology, I designed a high-gain CMOS differential amplifier achieving 84 dB DC gain, 64° phase margin, and 14 MHz UGB while driving a 150 pF load. I also designed and implemented an OTA-C based analog delay cell with 0.658 µs delay with 15 pF load using tunable transconductance, and contributed to circuit-level implementation of activation functions.

Through analog layout training, I designed and implemented DRC/LVS-clean full-custom layouts of current mirror, cascode current mirror, and single-stage op-amp using TSMC 45nm and 16nm PDKs. I apply matching-critical techniques including common centroid, interdigitation, multi-finger devices, and dummy devices, plus shielding and parasitic-aware routing for sensitive analog nodes. I also use guard rings and substrate isolation techniques to improve robustness and reduce substrate noise.