At Excelmax Technologies, I worked as a Lead layout Engineer, developing custom and memory layouts and writing Cadence SKILL scripts for layout automation. The scripts increased layout development speed by 30% to 40%.
I worked on SRAM row decoder, IO, and control blocks from scratch to chip level, as well as ECO implementation and physical verification. I also bring knowledge of memory architecture.
My analog and mixed-signal layout work included BGR and LDO modules, DLL modules, and SerDes blocks. I performed DRC, LVS, ERC, EM-IR, and antenna checks across technology nodes from 3nm GAA to 40nm.
Earlier, I worked as a Layout Design Engineer at Sankalp Semiconductor and a Design Engineer at Yoctozant Technologies. During my internship at Zia Semiconductor Pvt Ltd, I worked on standard cells libraries.
