At Wipro, I implement and verify custom layout ECOs and memory and analog blocks for Intel projects. On Intel 3nm ECO blocks, I added PMOS and NMOS devices and completed DRC and LVS verification.
For Intel's 5nm project, I designed D-latch, flip-flop, and full-adder layouts from scratch. I completed DRC, LVS, EM/IR, and ERC checks using ICV, CPDS, and Cheetah.
At Elbrus Labs Pvt. Ltd., I worked on SRAM-related custom layout and physical verification for the Synopsys client. I designed a 16nm FinFET level-shifter layout, created and verified its CHCELL view, and completed EM/IR and VERC checks.
My project work also includes a 7nm ROM control-block ECO, IO-cell layout for SMIC 40nm and HHGrace 40nm projects, and 90nm ICG and sense-amplifier layout. I use Cadence Virtuoso and Synopsys Custom Compiler alongside physical-verification tools.
