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vaibhav vaidyaVV
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vaibhav vaidya

@vaibhavvaidya1

Senior ASIC Design Engineer at NVIDIA who designed USB debug protocol RTL and led USB controller silicon bringup.

India
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At NVIDIA, I designed RTL for a unified debug protocol over USB, intended for server-class GPU, CPU, and networking silicon. I implemented the base protocol engine and two debug agents after resolving specification ambiguities with the architect.

I led USB device controller bringup for a next-generation CPU, supporting three firmware clients and management-traffic IPs. I developed a test plan covering 40+ scenarios and used logic-analyzer traces and scan dumps to trace a hardware failure to a buffer with an RDC issue.

I led the migration of USB host and device IP to synchronous resets across approximately 100 modules, reducing RDC verification time by approximately 3–4 weeks per downstream project. I also defined microarchitecture and implemented RTL for the USB device controller’s Target and Initiator interfaces.

Earlier at NVIDIA, I contributed to the USB device controller’s transition to a hardware-driven multi-function composite design and implemented RTL for its Port Event Handler. I debugged DMA and PIO interfaces, identifying the root causes of 50+ RTL bugs in simulation, and performed CDC, RDC, LEC/Formality, gate-level simulation, and X-propagation checks.

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Education

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Indian Institute of Technology, Bhubaneswar logoIB

Indian Institute of Technology, Bhubaneswar

B.Tech (Hons.), Electronics & Communication Engineering

Grade: 9.05/10

Completed B.Tech (Hons.) in Electronics & Communication Engineering with a CGPA of 9.05/10.

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