Srikar Maturi

I’m a Senior Hardware Engineer building and leading verification efforts across the full chip lifecycle, from pre-silicon RTL verification blocks to post-silicon validation. I develop UVM components and test bench blocks within the chip’s architectural framework, and I’ve created optimized flows for RTL, testbenches, and test-runners to improve design validation.

My work includes Memory Controller and DMA Sub-System verification for data integrity, plus Interrupt Controller and Communication Units verification for robust interrupt management. I implement processor sequences and firmware for Secure Boot, Control, Vector, and Xtensa processors, and I run comprehensive Interconnect (AXI) Verification with Access Control, ATUs, Error Responses, and Timeouts. I also verify XSPI, UART, and I2C peripherals, validate SBP’s boot process, handle Warm/Cold/Functional Reset processes for all partitions, and configure PLL settings for frequency and stability.

I strengthen quality through infrastructure and reliability work: I built reusable test cases for regressions, coverage, and emulation, and I develop gate-level simulation (zero-delay) testcases for logical and spatial netlist validation. I perform UPF low-power verification, manage DFT bring-up with BIST/BISR verification, and run ATE and SDF simulations for timing accuracy post-silicon. Most importantly, I lead post-silicon validation for assigned blocks, develop firmware/system APIs for hardware-software integration, and create internal tools to accelerate DDR training, PCIe power optimization, and debug/turnaround time.