shivraj singh
@shivrajsingh
Experienced Research & Development Engineer specializing in power analysis.
IndiaWhat I'm looking for
I am a dedicated Research & Development Engineer with extensive experience in optimizing power analysis tools and enhancing circuit functionality. Currently, I work at Synopsys India, where I have successfully reduced the runtime of SAIF file processing by 85%, significantly improving efficiency in power analysis. My role involves implementing innovative solutions, such as power checksum support in Fusion Compiler, which enhances reliability and traceability in power analysis.
Previously, I contributed to X-Epic Technology Co. Ltd, where I led a team to develop a solution for verifying circuit equivalence using SAT solver algorithms. My work included integrating low-power functionality into designs and resolving customer issues through effective project management. I am passionate about leveraging my technical skills to drive advancements in electronic design automation and contribute to impactful projects.
Experience
Work history, roles, and key accomplishments
Research & Development Sr. Engineer
Synopsys India
Jan 2024 - Present (1 year 7 months)
Optimized SAIF file processing, reducing read_saif command runtime by 85%, improving efficiency in power analysis. Implemented power checksum support in Fusion Compiler to diagnose and debug non-determinism issues, improving reliability and traceability of power analysis.
Research & Development Engineer 2
X-Epic Technology Co. Ltd
Dec 2021 - Dec 2023 (2 years)
Implemented a translator that seamlessly converts compiler-generated abstract syntax trees into a unified object-oriented database format, facilitating efficient data sharing across diverse products. Integrated low-power functionality into the functional design of the Low-Power simulator, resolved customer Jira issues and added support for UPF commands.
Research & Development Engineer
X-Epic Technology Co. Ltd
May 2021 - Nov 2021 (6 months)
Engineered and implemented an algorithm in C++ for combinational loop detection in Flatnetlist, significantly accelerating the analysis process. Developed and implemented an algorithm to identify the minimal set of break points in a Flatnetlist, effectively disrupting all loops and optimizing circuit functionality.
Education
Degrees, certifications, and relevant coursework
Indian Institute of Information Technology, Kota
Bachelor of Technology, Electronics and Communication Engineering
2017 - 2021
Grade: 8.85
Completed a Bachelor of Technology in Electronics and Communication Engineering. Achieved a GPA of 8.85.
Tech stack
Software and tools used professionally
Availability
Location
IndiaAuthorized to work in
Job categories
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