At Qualcomm, I work on UPF-based power implementation for Hexagon DSP cores, including the Neural Signal Processor. I develop power intent from the power specification and support multi-voltage design implementation throughout the RTL-to-GDS flow.
I address synthesis issues involving multi-voltage cells such as isolation, level shifters, and retention. I also work with SoC and subsystem teams on power-intent handoffs and dynamic and leakage power figures.
Before Qualcomm, I worked at Cadence Design Systems on synthesis product validation. I created test plans for low-power features and validated power intent at the synthesis gate level.
Across these roles, I’ve worked with UPF and power-design tools, and I develop automation workflows using Python, Tcl, and generative AI.
