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Pratham Shetty

@prathamshetty1

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I build efficient hardware accelerators and machine learning systems for RISC-V, LLMs, and wireless communications.

India

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What I'm looking for

I'm looking to build efficient hardware and machine learning systems, especially for RISC-V processors, LLM inference, VLSI design, and signal-processing applications.

I've developed hardware accelerators at IIIT Bangalore, including a unified MXFP4/NVFP4 MAC co-processor for PicoRV32 and CV32E40P that achieved 40.2x speedup over a soft-float baseline. My work also includes a CORDIC-based RoPE accelerator for LLMs, reducing area by up to 31.4% and power by 64.5%.

I've applied machine learning and signal processing to physiological-signal intermapping, massive-MIMO CSI feedback, and visual product retrieval. I work across C, C++, Verilog, Python, MATLAB, ASIC design flows, and tools including Vivado and Cadence Virtuoso.

Experience

Work history, roles, and key accomplishments

Summer Research Intern

IIIT Bangalore

May 2026 - Jul 2026 (2 months)

Devised a unified dual-mode MAC accelerator for RISC-V processors supporting both MXFP4 and NVFP4 in a single datapath. Integrated the co-processor into PicoRV32 and CV32E40P cores, achieving significant speedup and code-size reduction.

RISC V MAC Accelerator MXFP4 NVFP4 PicoRV32 CV32E40P PCPI APU 45nm ASIC TinyLlama WikiText 2

Research Intern

IIIT Bangalore

May 2025 - Jul 2025 (2 months)

Analyzed physiological signals by establishing various machine learning models to understand the interrelationship and mapping using Photoplethysmogram (PPG) data. Focused on signal processing and predictive modeling to explore correlations among physiological parameters.

Machine Learning Signal Processing Photoplethysmogram predictive modeling