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crazy buddy

@crazybuddy

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Lead FPGA RTL design engineer specializing in FPGA micro-architecture, verification, and end-to-end hardware solutions.

India

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What I'm looking for

I’m looking for a Lead FPGA/RTL role where I can drive micro-architecture, verification, and HW/SW integration, lead projects, and deliver low-latency FPGA systems with strong bring-up and debug support.

I’m a Lead FPGA Design Engineer with 8.10 years of experience as an FPGA-RTL Design Engineer, focused on turning design specifications into working FPGA systems. I lead projects end-to-end—delegating tasks, motivating peers and juniors, and driving implementation with clear prioritization.

I create micro-architecture from requirements and build FPGA-RTL firmware using Verilog and System Verilog/VHDL. I integrate FPGA-developed modules with RTL/IPs to deliver system level solutions, including memory modeling, configuration modules, and protocol modeling.

Across ultrasound and other embedded domains, I’ve redesigned micro-architecture and developed RTL algorithms/protocol/interface modules for platforms like Lotus (neurotechnology), Shasta/Shasta-v2 (breast cancer detection), Granite and OMT (ultrasound detection), and Gen-0B. I develop test plans, run verification and validation on modelsim and on hardware (oscilloscope/board bring-up), and optimize FPGA resource usage and performance.

To ensure robust delivery, I work closely with HW/SW teams for end-to-end solutions and provide bring up, debug/verification, and validation support. I’m also comfortable with scripting and tooling—shell scripting, tcl scripting, and C—so I can define and execute tasks with limited direction, troubleshoot effectively, and solve complex technical problems.

Experience

Work history, roles, and key accomplishments

Current

Lead FPGA Design Engineer

Current

A & W Engineering Works

May 2018 - Present (8 years 2 months)

Led FPGA-RTL design projects, including micro-architecture creation, Verilog/SystemVerilog firmware development, and verification. Integrated FPGA modules with RTL/IPs and delivered system-level solutions across custom interfaces and bring-up/debug activities.

Verilog ModelSim CRO SPI I2C HyperRAM DDR3 PCIe DDR Memory Interface Bridge Debugging Tcl Shell Scripting C#Gitlab

FPGA Design Engineer

Unizen Technologies Pvt Ltd

Oct 2016 - May 2018 (1 year 7 months)

Developed FPGA firmware and RTL for multiple products, handling micro-architecture design, protocol/interface implementation, and verification. Worked across FPGA tools and debug flows to validate designs on target hardware.

FPGA Design Verilog ModelSim ChipScope CRO Shell Scripting Tcl SPI TCP UDP USB 2.0 With Synchronous FIFO Automated Testbench Scripting

Trainee Engineer

Sandeepani Institute of Vlsi

Feb 2016 - Oct 2016 (8 months)

Performed FPGA RTL design and verification work as a trainee, including implementing a VGA controller and a round robin arbiter. Verified and validated designs on Spartan 3E hardware and in simulation.

Verilog Spartan 3E VGA Controller ModelSim ChipScope