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Ram kumar User

@ramkumaruser2

Aspiring ASIC Design Verification engineer with SPI and Router 1x3 verification projects using SystemVerilog testbenches and assertions.

India

Message

What I'm looking for

I'm seeking an entry-level opportunity in ASIC Design Verification or RTL Design, where I can contribute to functional verification and SoC-level test infrastructure for digital designs.

At TVS Motor Company Ltd, I reviewed customer complaints and product-quality feedback, routed identified issues to the responsible teams, and tracked corrective actions through resolution.

In my SPI Verification project, I designed and executed a SystemVerilog testbench for an SPI Master RTL design. I developed directed tests for full-duplex communication and used SVA to check protocol compliance with multiple serial slaves.

For my Router 1x3 project, I structured a design that routes packets from one 8-bit input to three destinations and wrote tests across the output channels. I also worked on a Li-Fi wireless data-transfer system, implementing timing control for message transmission.

Experience

Work history, roles, and key accomplishments

Graduate Apprentice Trainee

TVS Motor Company Ltd

Reviewed customer complaints and feedback on product quality, analyzing issues to identify root causes. Routed identified issues to responsible teams and tracked resolution to closure, supporting the plant's quality management process.

Quality Management Root Cause Analysis Documentation Cross Functional Communication Problem Solving