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Chinmayi M

@chinmayim

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I build neuromorphic mixed-signal ASICs, from IC layout and verification through tape-out and post-layout validation.

India

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At IISc's MoNC-AI Lab, I contribute to ultra-low-power neuromorphic mixed-signal ASICs for molecular memristive AI hardware, spanning circuit implementation, IC layout, physical verification, and post-layout validation.

I previously supported tape-out at IISc CeNSE, translating schematics into manufacturable layouts and resolving DRC, LVS, PEX, and post-layout simulation issues. I also build embedded systems using Arduino, sensors, Python, GPIO, and microcontrollers.

Experience

Work history, roles, and key accomplishments

Current

Project Research Associate

Current

Indian Institute of Science (IISc)

Jul 2025 - Present (1 year 2 months)

Contribute to the design of ultra-low-power neuromorphic mixed-signal ASICs for AI hardware built on molecular memristive devices. Perform DRC, LVS, and parasitic extraction (PEX) in Cadence and Calibre to support physical verification and design closure.

Mixed Signal IC Design CMOS Circuit Design ASIC Physical Design IC Layout Physical Verification DRC LVS PEX Virtuoso Calibre Neuromorphic Computing In Memory Computing

Project Research Intern

Indian Institute of Science (IISc)

Nov 2024 - Jun 2025 (7 months)

Contributed to the tape-out of a neuromorphic mixed-signal ASIC. Executed key stages of the ASIC physical design flow, including layout implementation, DRC/LVS verification, and parasitic extraction.

ASIC Physical Design Layout Implementation DRC LVS Parasitic Extraction Post Layout Simulation Virtuoso Calibre Mixed Signal IC Design

Cybersecurity Intern

SenseLearner

Sep 2023 - Nov 2023 (2 months)

Analyzed system vulnerabilities using structured debugging and problem-solving approaches. Worked in Linux-based environments for system-level analysis and troubleshooting.

Cybersecurity Vulnerability Analysis Debugging Linux System Analysis Troubleshooting