Open to opportunities

Anindita Chattopadhyay

@aninditachattopadhya1

Message

I build GNN-based hardware security verification and real-time FPGA intrusion detection systems.

India

Message

What I'm looking for

I'm seeking a PhD position to advance hardware security, side-channel and fault-injection analysis, and trustworthy AI systems for chip and system verification.

At ADE/DRDO, I've built graph neural network pipelines that turn raw Verilog netlists into RTL- and gate-level hardware Trojan detection and localization models. My work has resulted in four peer-reviewed IEEE and Springer publications, including an ICCC 2025 Best Paper award.

I've also designed a deterministic FPGA-based intrusion detection system for ARINC-825 avionics buses, delivering 40 ns latency at 100 MHz on a Xilinx Zynq-7020. The design distinguishes cyberattacks from hardware faults through dual-channel redundancy and was verified across 10 adversarial and fault-injection scenarios with a 100% pass rate.

Before research, I automated enterprise network diagnostics and provisioning at Accenture, reducing provisioning time by 30%. I'm seeking to extend my work in hardware security, side-channel and fault-injection analysis, and trustworthy AI for chip and system verification.

Experience

Work history, roles, and key accomplishments

Current

Research Engineer

Current

Aeronautical Development Establishment (ADE), DRDO

Dec 2022 - Present (3 years 8 months)

Designs and trains Graph Neural Network models for hardware Trojan detection in RTL and gate-level netlists. Built an end-to-end pipeline from raw Verilog to GNN classification and published 4 peer-reviewed papers.

Verilog RTL Netlist Hardware Security Deep Learning Classification ModelSim GTKWave

Network Associate

Accenture

May 2018 - Mar 2020 (1 year 10 months)

Automated fault diagnostics and reporting for enterprise networks, reducing provisioning time by 30% through toolchain optimization. Managed activation and configuration of enterprise network circuits and performed circuit-level debugging and root cause analysis.

Network Operations Automation Debugging Root Cause Analysis Provisioning

FPGA-Based Intrusion Detection System

Aeronautical Development Establishment (ADE), DRDO

Designed a deterministic real-time hardware detection pipeline in Verilog achieving 40ns latency at 100MHz on Xilinx Zynq-7020 SoC. Engineered a dual-channel redundancy correlator distinguishing cyberattacks from hardware faults with zero misclassification.

Verilog FPGA Zynq 7020 Real Time Systems Hardware Security GTKWave