veda s
@vedas
RTL/ASIC Design Engineer specializing in RTL quality, CDC sign-off, and SoC integration.
IndiaWhat I'm looking for
I’m an RTL/ASIC Design Engineer with 9+ years of experience in RTL design quality, SoC integration, and front-end sign-off methodologies across complex SoC programs at Intel and Samsung. I focus on getting clean RTL handoff to physical design through disciplined verification and sign-off readiness.
I bring strong RTL quality expertise in Lint, CDC, synthesis validation, and constraint development. I use industry-standard static analysis to find structural issues, unsafe clock domain crossings, and timing constraint problems—and then drive fixes through to closure.
My work consistently includes debugging RTL structural violations, resolving synchronization and reconvergence issues, and validating reset domain crossing (RDC) and reset synchronization methodologies. I also improve team velocity through SDC constraint development, Tcl scripting, and flow automation for better runtime efficiency.
Beyond sign-off, I’ve supported SoC and integration workflows such as top-level connectivity and IP integration using DeFacto, Dealing with hierarchical connectivity and interface mapping across large-scale designs. I’ve also maintained and debugged RTL methodology infrastructure (Cheetah, R2G), ensuring Lint/CDC and synthesis validation environments run reliably for design teams.
Experience
Work history, roles, and key accomplishments
Executed lint and CDC sign-off checks for SoC using VC CDC, validating clock/reset domain crossing safety and synchronization methodology for tape-out readiness. Debugged CDC report violations with RTL/design teams and reviewed waiver justifications to close CDC/RDC issues within timelines.
Performed top-level SoC integration of multiple IP blocks using DeFacto, ensuring correct connectivity across hierarchical modules. Managed ad-hoc connectivity and IP version updates, maintained connectivity models/interface mappings, and resolved integration mismatches with RTL and verification teams.
Conducted static RTL quality analysis and CDC verification for sign-off using SpyGlass Lint/CDC, focusing on structural issues and unsafe clock domain crossings. Supported both front-end and back-end verification/synthesis validation flows by troubleshooting tool/environment errors to maintain quality standards and improve runtime efficiency.
Maintained and debugged RTL Tools/Flows/Methodology (TFM) infrastructure to support lint, CDC, and synthesis validation runs. Set up and optimized Cheetah environments, performed top/leaf lint checks with SpyGlass, and resolved RTL violations and environmental/runtime issues with design teams.
Performed lint and CDC sign-off checks for IP blocks using SpyGlass and ensured compliance with project coding guidelines. Debugged RTL structural violations, verified clock domain crossing safety, and supported synthesis validation for backend readiness.
Performed RTL quality checks using lint and CDC tooling for high-speed serial interface IP, analyzing reports for structural issues and unsafe clock domain crossings. Collaborated with designers to resolve violations and achieve clean RTL sign-off before synthesis.
Hermes Synthesis
In-House
Apr 2017 - Dec 2017 (8 months)
Performed RTL-to-gate-level synthesis and constraint sanity checks, supporting timing/area goals and SDC verification for clocking and paths. Conducted linting/debugging with SpyGlass and collaborated with RTL teams to resolve CDC setup issues and violations.
Education
Degrees, certifications, and relevant coursework
Lords Institute of Engineering & Technology
Master of Technology (M.Tech)
Earned an M.Tech from Lords Institute of Engineering & Technology (JNTUH), graduating in 2011.
Tech stack
Software and tools used professionally
Availability
Location
IndiaAuthorized to work in
Job categories
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