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Muhammad Sarmad Sohail

@muhammadsarmadsohail

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Electrical engineer and data engineer blending IC design with ML and generative AI.

Pakistan

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What I'm looking for

I seek roles that combine IC/hardware design and ML/data engineering in collaborative teams, focusing on impactful, production-grade systems and research-driven innovation.

I am an electrical engineer with hands-on experience in analog & mixed-signal IC design and data engineering, combining Cadence and Synopsys-based chip design with production-grade Python backend and PySpark ETL development.

I’ve published research at IEEE WCNC 2024 on DRL-driven resource allocation for MEC-enabled CR-NOMA networks and built DRL, CNN-LSTM, and generative AI projects, earning top-performer recognition in a Generative AI training cohort.

I deliver practical, scalable solutions—from designing SAR ADCs and RFID transponders in CMOS technologies to implementing FastAPI microservices, synthetic data pipelines, and deep RL frameworks—aiming to bridge hardware and ML systems for real-world impact.

Experience

Work history, roles, and key accomplishments

Current

Data Engineer

Current

Adept Tech Solutions

Sep 2025 - Present (3 months)

Develop and maintain backend microservices and production-grade modules for the ASCEND Synthetic Data Platform, and orchestrate distributed PySpark ETL workloads to enable scalable synthetic data generation across large datasets.

Python fastAPI Pyspark ETL Synthetic Data Generation Anonymization Imputation

GenAI Trainee

Pak Angels

Jun 2025 - Jul 2025 (1 month)

Completed intensive Generative AI training covering ChatGPT APIs, LangChain, RAG systems, and autonomous agents; delivered weekly projects and was awarded Top Performer in the cohort.

Generative AI Lang Chain RAG Python Autonomous

Trainee Engineer - AMS IC Design

Xcelerium

Jan 2025 - May 2025 (4 months)

Designed SAR ADC prototypes (100 MHz 7-bit in TSMC 28nm and 12-bit high-speed in GF 22nm FD-SOI), and streamlined AMS design workflows to improve standardization in Synopsys environments.

Synopsys Custom Compiler SAR ADC Design CMOS PDKs

Analog & Mixed Signal Trainee

NUST Chip Design Centre

Jul 2024 - Nov 2024 (4 months)

Gained hands-on experience in MOS device behavior, schematic/layout design using Cadence Virtuoso, and participated in design and sign-off of analog blocks and a passive RFID transponder chip in CMOS 65nm.

Layout PLL CMOS 65nm

Research Intern

Information Processing & Transmission Lab

May 2023 - May 2024 (1 year)

Designed and implemented a DDPG framework integrating MEC and CR-NOMA for dynamic resource allocation in energy-harvesting IoT networks, publishing results at IEEE WCNC 2024 with faster convergence and reduced service delay versus baselines.

Python TensorFlow Simulation MEC CR NOMA

Research Intern

CNN Internship, SEECS

Jun 2023 - Aug 2023 (2 months)

Developed Conv2D+LSTM architectures for video-based regression on the UBFC dataset, implemented preprocessing and augmentation pipelines to improve model training and robustness.

Python PyTorch Keras Video Dataset Augmentation Video Processing NumPy

Education

Degrees, certifications, and relevant coursework

National University of Sciences and Technology (NUST)

Bachelor of Electrical Engineering, Electrical Engineering

2020 - 2024

Grade: CGPA: 3.70/4.00

Activities and societies: Key courses: Mobile Communication Systems, Machine Learning, Digital Signal Processing, Embedded System Design, Robotics, Digital System Design, Probability & Statistics; thesis, paper, demo, poster.

Bachelor of Electrical Engineering with a 3.70/4.00 CGPA; thesis on resource allocation for MEC-enabled CR-NOMA networks using deep reinforcement learning and advised by Dr. Syed Ali Hassan.