At Defence Electronics Application Laboratory (DEAL), DRDO, I studied and implemented Non-Offset QPSK and other modulation schemes for reliable data transmission. I used MATLAB to simulate signal generation, symbol mapping, and constellation diagrams, and evaluated bandwidth, power efficiency, and bit error rate under different noise conditions.
For my low-power 6T-SRAM project, I designed and simulated a cell in Cadence Virtuoso using 180nm gpdk CMOS. I evaluated hold, read, and write operations, optimized transistor sizing, and analyzed stability using Static Noise Margin butterfly curves.
At Indian Institute of Technology (IIT) Mandi, I designed a seventh-order active bandpass filter using cascaded Sallen-Key stages and simulated its performance in LTspice. I’m interested in VLSI design and simulation, and I’ve also developed Arduino-based safety and sensor prototypes.
