Ishan Ishan

In a faculty-facilitated university training programme, I designed and simulated a transistor-level two-stage CMOS op-amp in Cadence Virtuoso, including its differential amplifier, current mirror, and biasing sub-blocks. I evaluated its performance with DC, AC, and transient analyses, and validated it across PVT corners and with Monte Carlo analysis.

The op-amp achieved about 70 dB DC gain, about 80 MHz gain-bandwidth, and more than 60° phase margin. I also worked on a multiplier design in Cadence as part of research.

I designed and simulated a CMOS bandgap reference using PTAT and CTAT components, producing a reference output of about 1.2 V with low temperature sensitivity. I’m currently studying LDO regulator design, including its operating physics, simulation, and calculation checks.

Alongside analog design, I designed and verified an ALU and UART transmitter/receiver in Verilog HDL using Xilinx Vivado. My other projects include a low-power approximate adder and ALU for my thesis, an LM2596 power-supply PCB, and an ESP32 wireless sensor data-acquisition system.