At IIT Bhubaneswar, my M.Tech thesis focuses on optimizing and innovating BCD arithmetic units with an added layer of fault tolerance, blending performance and reliability in modern digital systems.
Iām specializing in Digital VLSI Design, with a background in semiconductor devices, digital CMOS VLSI, and digital IC architecture.
I enjoy hands-on work with Cadence Virtuoso and Vivado.
I worked part-time as a Teaching Assistant at IIT Bhubaneswar from August 2024 to May 2026. Earlier, I was a Graduate Trainee Engineer at Cubastion Consulting and an Intern at TATA Power.
