At Qualcomm, I analyze camera subsystem and visual accelerator performance across mobile and automotive SoCs, using TLM traffic simulation to identify bandwidth and latency bottlenecks. I've built dashboards for camera use cases and automated bottleneck-analysis workflows, reducing manual debug effort by 25%.
Previously at NXP Semiconductors, I modeled and validated DDR memory controllers, improved LPDDR5 worst-case latency by 4%, and achieved 95% correlation between cycle-accurate DDR models and RTL. I work across interconnect, memory, and SoC architecture using FlexNoc, Platform Architect, SystemC, C++, and Python.
