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Vaishnavi Joshi

@vaishnavisjoshi

I build high-performance systems spanning GPU kernels, parallel computing, embedded firmware, and computer architecture.

United States

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What I'm looking for

I'm seeking a full-time role in systems, embedded, GPU performance, or computer architecture engineering where I can build and optimize high-performance software, hardware, and computing systems.

I'm pursuing an MS in Electrical and Computer Engineering at Northeastern University, focused on computer systems, HPC, and embedded systems. I build performance-oriented software and hardware projects across GPU computing, parallel systems, FPGA acceleration, and low-level firmware.

For cache-aware and GPU-accelerated SpMV, I built CPU kernels using cache tiling, AVX2 SIMD, and software prefetching, achieving an 18% tiling speedup and 30% AVX2 gain over baseline. I also developed CUDA kernels on an NVIDIA A100, with a vector kernel reaching 98–110% of HBM2 peak bandwidth and outperforming cuSPARSE by 24–56%.

I've built an NFS-like distributed file server in Rust with scheduler-based write locking, where MLFQ and CFS policies delivered 1.6x throughput and a 5.8x latency reduction over FIFO under contention. My systems work also includes a five-stage pipeline simulator, MPI+OpenMP Mandelbrot rendering, and a contextual-bandit WiFi packet scheduler.

At Foxconn, I helped launch the Bengaluru iPhone plant and coordinated a 120-operator assembly line, increasing output from 22% to 83.4% through bottleneck diagnosis and defect-mode training. As a Northeastern teaching assistant, I've supported courses in algorithms, computer architecture, and electronics labs while giving technical feedback on programming, hardware, and circuit design.

Experience

Work history, roles, and key accomplishments

Teaching Assistant, Fundamentals of Electronics/Lab

Northeastern University

Jun 2026 - Aug 2026 (2 months)

Delivered weekly recitation and lab instruction for a Summer II cohort, guiding op-amp, diode, BJT, and MOSFET circuit builds validated with oscilloscope, function generator, DC supply, DMM, and curve tracer measurements. Graded assignments and exams on large/small-signal transistor models, frequency response, and CMOS logic design, holding office hours to reinforce circuit-analysis fundamentals.

Electronics OPAMPs Diodes BJT MOSFET Oscilloscopes Circuit Analysis CMOS

Teaching Assistant, Computer Architecture

Northeastern University

May 2026 - Jun 2026 (1 month)

Assessed student mastery of processor-level concepts and hardware-software interfaces, grading technically dense assignments spanning ISA design, pipelining, and virtual memory systems. Appraised architectural design submissions for hardware optimization, scrutinizing student analysis of cache efficiency, memory hierarchy, and superscalar execution strategies.

Computer Architecture ISA (Instruction Set Architecture)Pipelining Virtual Memory Cache Optimization

Teaching Assistant, Fundamentals of Engineering Algorithms

Northeastern University

Jan 2026 - Apr 2026 (3 months)

Evaluated algorithmic reasoning and graded technical quizzes for a large student cohort, enforcing rigorous rubric standards while delivering targeted feedback on data structure design and algorithmic correctness. Dissected student code submissions for edge-case robustness and complexity trade-offs, translating logical flaws into actionable feedback.

Algorithms Data Structures Grading Feedback Technical Communication

Graduate Trainee Engineer

Foxconn Hon Hai Technology India Mega Development Pvt Ltd

Nov 2023 - Oct 2024 (11 months)

Among the founding production team launching Foxconn's new Bengaluru iPhone plant, deployed after 6 months of cross-functional manufacturing training at Foxconn Chennai. Coordinated a 120-operator assembly line, diagnosed station-level bottlenecks, and drove output rate from 22% to 83.4% by leading 7 training sessions on defect modes and root-cause analysis.

Manufacturing Assembly Line Management Root Cause Analysis Training Process Optimization