I built an 8-bit pipelined processor in Verilog with hazard detection and implemented it on FPGA using Xilinx Vivado. My projects also include an AMBA APB4 monitoring IP core and a Python tool that automates Yosys synthesis and netlist SVG generation.
During my Microchip Embedded Systems Developer Intern role with AICTE–EduSkills, I completed a PIC16 track covering embedded C, BLE app development, and Azure IoT sensor nodes. I’ve also analyzed data and built dashboards at Elevate Labs, and developed Android app modules at EduSkills Foundation.

