I've built FPGA, RTL, and embedded systems that connect real-time sensing with practical monitoring and automation. My work spans Verilog-based digital design, custom RISC-V-inspired CPU development, and analog circuit design.
During my internship at IVW Pvt Ltd, I worked on an RFID-based warehouse monitoring system with a line-follower robot and built a Python interface for real-time entry and exit logging. I also designed a custom 16-bit RISC-V-inspired CPU on a Sipeed Tang Nano 20K FPGA for wound temperature and moisture monitoring.
I'm an Electronics and Communication Engineering student at SRM IST and a Samsung ISWDP semiconductor workforce fellow. I have trained in Cadence digital design, verification, and design-for-testability flows, and published IEEE research on EV charging compensation circuits.
