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Sakshi GalleSG
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Sakshi Galle

@sakshigalle

VLSI Research Intern at IIIT Dharwad simulating semiconductor devices with Synopsys Sentaurus TCAD in Linux.

India
Message

At Indian Institute of Information Technology Dharwad (IIIT Dharwad), I’m working on semiconductor device simulation using Synopsys Sentaurus TCAD in a Linux environment. This ongoing research internship is giving me hands-on experience with device modeling and simulation workflows.

In my LVEC project, I designed an Edge AI-based wildlife collision prevention system using a Tang Nano 4K FPGA for real-time object detection. I implemented LoRa-based V2I communication and integrated an Arduino Nano, LCD display, and buzzer for real-time alerts in an offline architecture.

During VLSI Design training with Internshala Trainings, I learned Verilog HDL, RTL design methodology, and FPGA implementation. I’ve also designed and simulated digital circuits with Verilog HDL, Icarus Verilog, and GTKWave.

Experience

Work history, roles, and key accomplishments

Indian Institute of Information Technology Dharwad logoID
Current

VLSI Research Intern

Indian Institute of Information Technology Dharwad

Aug 2026 - Present (3 months)

Working on semiconductor device simulation using Synopsys Sentaurus TCAD. Gaining hands-on experience in device modeling and simulation workflows in a Linux environment.

Internshala Trainings logoIT

VLSI Design Trainee

Internshala Trainings

Feb 2025 - Apr 2025 (2 months)

Completed an 8-week VLSI Design training program covering Verilog HDL, RTL design methodology, combinational and sequential circuits, FSM design, FPGA implementation, and basic verification concepts.

Education

Degrees, certifications, and relevant coursework

JV

Jain College of Engineering, VTU

Bachelor of Engineering, Electronics and Communication Engineering

2023 -

Grade: 8.15

Pursuing a Bachelor of Engineering in Electronics and Communication Engineering with a CGPA of 8.15.

IT

Internshala Trainings

VLSI Design Training, VLSI Design

2025 - 2025

Completed an 8-week VLSI Design training program covering Verilog HDL, RTL design, and FPGA implementation.

RC

Raja Lakhamagouda Science PU College

Pre-University, PCMB

2021 - 2023

Completed Pre-University education with a focus on Physics, Chemistry, Mathematics, and Biology.

UD

Udemy

Complete 2025 Guide: Embedded Systems from Scratch, Embedded Systems

Completed the Complete 2025 Guide: Embedded Systems from Scratch course.

VI

VTU Hardware Security Program (MeitY & ISEA)

VTU Hardware Security Program, Hardware Security

Completed the VTU Hardware Security Program organized by MeitY and ISEA.

CT

ChipExpert Technology

VLSI Design Workshop, VLSI Design

2025 - 2025

Attended the VLSI Design Workshop by ChipExpert Technology on 9 September 2025.

ID

IIIT Dharwad

Advanced VLSI Workshop, VLSI

2025 - 2025

Attended the Advanced VLSI Workshop at IIIT Dharwad from 28 July to 1 August 2025.

IS

ISRO

Space Science & Technology Awareness Training (START), Space Science and Technology

Completed the ISRO Space Science and Technology Awareness Training (START).

Tech stack

Software and tools used professionally

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