Open to opportunities

Andrew Chen

@andrewchen5

Message

FPGA team lead delivering real-time, timing-closed video and audio systems.

United States

Message

What I'm looking for

I’m seeking an FPGA leadership role where I can drive architecture-to-release delivery, mentor engineers, and ensure timing-closed, high-throughput PCIe/DDR pipelines for real-time media systems on Linux and Windows.

I’m an FPGA Team Lead with 8 years of experience delivering high-performance FPGA solutions for real-time video, audio, and embedded processing systems. I specialize in SystemVerilog/Verilog, FPGA system architecture, PCIe, DDR4/DDR5, and timing closure across both AMD (Xilinx) and Intel FPGA platforms.

I lead end-to-end FPGA development—architecture definition, RTL implementation, verification, synthesis, place-and-route optimization, and production releases for Linux and Windows-based embedded products. I design high-speed data processing pipelines using transceivers, clock-domain crossing strategies, arbitration logic, and memory interfaces, and I coordinate teams through code inspections, task allocation, and release management to maintain quality, schedule, and technical excellence.

Experience

Work history, roles, and key accomplishments

Current

Senior FPGA Design Engineer

Current

BAE Systems, Inc

Jan 2022 - Present (4 years 5 months)

Architected FPGA subsystems for real-time video and audio processing, supporting multi-Gbps streaming workloads across 4 production product lines. Integrated PCIe and DDR4 achieving sustained data movement above 8 Gbps, built 250 MHz SystemVerilog RTL, and improved pre-integration defect detection by 35% using 300+ automated regression tests while reducing post-release FPGA defects by 25%.

RTL Design PCIe DDR4 Regression Testing

FPGA Team Lead Engineer

Logicircuit, Inc

Jul 2019 - Dec 2021 (2 years 5 months)

Led an FPGA team of 5 engineers across concurrent projects, defining design methodologies and review processes used across 6 active development programs. Managed quarterly Linux/Windows release builds, provided technical leadership for PCIe/DDR5/transceiver architectures above 10 Gbps, mentored engineers, and reduced FPGA implementation turnaround time by 20% while improving build consistency.

FPGA Team Leadership RTL Design PCIe High Speed Transceivers Release Management