At Synopsys Inc, I plan and develop C++/SystemC IPs and processor models, integrating them into Platform Architect and Virtualizer. I also improve virtual-platform simulation performance, achieving more than 5x improvement for production software running on simulation platforms.
I led development of the Renesas G4MH processor simulation model using Imperas and mentored project members. I also integrated SiFive and Andes models, designed RISC-V CPU subsystems and OS-ready example platforms, and helped establish third-party core integration flows.
