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Arzoo Yadav

@arzooyadav1

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I build and verify Verilog digital designs, including clocking, counters, finite-state machines, and testbenches.

India

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I've built and simulated Verilog digital systems including a programmable digital alarm clock and a finite-state-machine traffic light controller. My work covers clock dividers, counters, registers, rollover logic, alarm comparison logic, reset handling, and state transitions.

I write testbenches with directed test vectors to validate edge cases, output timing, reset behavior, and expected waveforms. Through my Electrical Engineering coursework at IIT (ISM) Dhanbad, I've strengthened my foundation in computer programming, signals and systems, numerical methods, data structures, and algorithms.

I've solved 200+ Data Structures and SQL problems on LeetCode, ranked in the top 1% among 1.3 million+ JEE Main and Advanced candidates, and bring team leadership from representing and captaining IIT (ISM) Dhanbad football teams.

Experience

Work history, roles, and key accomplishments

Digital Alarm Clock

Indian Institute of Technology (Indian School of Mines) Dhan

Designed a digital alarm clock in Verilog with clock-divider, counters, and rollover logic. Added programmable time registers and alarm comparison logic, and verified via testbench simulation.

Verilog Digital Design Counters