At IIT Kharagpur, I integrated a custom AES-128 hardware accelerator into Rocket Core and implemented a three-instruction custom ISA extension. I synthesized the design onto a Nexys A7 100T FPGA and verified the instructions with bare-metal C scripts.
On my self-directed RISC-V CPU project, I designed a five-stage RV32I pipeline with a UART bootloader and validated it with custom assembly programs. I’ve also worked on a delta-sigma ADC modulator and filter design, modeling circuit non-idealities in MATLAB/Simulink.
