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Abhishek Panchal

@abhishekpanchal1

VLSI Design Intern at Nexus Core Innovation who developed a 5-stage pipelined RISC-V processor in Verilog.

At Nexus Core Innovation, I developed a 5-stage pipelined RISC-V RTL architecture in Verilog, with modular datapath and control logic for ASIC synthesis. I verified pipeline functionality through hazard detection, forwarding, RTL simulation, waveform debugging, and timing-critical path analysis.

As a Research Intern at DRDO, I fabricated and characterized thermoplastic composite specimens for defence applications. I analyzed their thermal and mechanical properties using laboratory instruments and documented the results for material performance evaluation.

Experience

Work history, roles, and key accomplishments

DO

Research Intern

DRDO (Defence Research and Development Organisation)

Feb 2026 - Jun 2026 (4 months)

Fabricated and characterized multiple thermoplastic composite specimens for defence applications using standardized laboratory procedures at DRDO-DEBEL. Analyzed thermal and mechanical properties using TGA, DSC, DMTA, UTM, and SEM, and documented experimental results for material performance evaluation.

Thermoplastics TGA DSC DMTA UTM SEM Material Characterization Laboratory Procedures

NI

VLSI Design Intern

Nexus Core Innovation

Feb 2026 - May 2026 (3 months)

Developed a 5-stage pipelined RISC-V RTL architecture in Verilog HDL with modular datapath and control logic for ASIC synthesis. Verified pipeline functionality through hazard detection, forwarding, RTL simulation, waveform debugging, and timing-critical path analysis.

Verilog RTL Design RISC V Logic Synthesis Hazard Detection Forwarding RTL Simulation Waveform Debugging Static Timing Analysis

Education

Degrees, certifications, and relevant coursework

ST

Sir M. Visvesvaraya Institute of Technology

Bachelor of Engineering, Electronics and Telecommunication Engineering

2022 - 2026

Grade: 8.28 CGPA

Pursued a Bachelor of Engineering in Electronics and Telecommunication, achieving a CGPA of 8.28.

DK

Dr. Channabasaveshwar Gurukul Residential/Non-Residential Pre University College Kardyal

Senior Secondary Education, PCMB

2020 - 2022

Grade: 85.5%

Completed Senior Secondary Education (PCMB) with a grade of 85.5%.

SS

Shree Swaminarayan Gurukul International School

Secondary Education, CBSE

2012 - 2020

Grade: 88%

Completed Secondary Education (CBSE) with a grade of 88%.

NP

NPTEL

VLSI Design Flow: RTL to GDS, VLSI Design Flow

Completed the NPTEL certification in VLSI Design Flow: RTL to GDS.

NI

NIELIT

VLSI for Beginners, VLSI

Completed the NIELIT certification in VLSI for Beginners.

ME

My Equation

Robotics and AI, Robotics and AI

Completed the My Equation certification in Robotics and AI.

UD

Udemy

PCB Design with KiCad, PCB Design

Completed the Udemy certification in PCB Design with KiCad.

Tech stack

Software and tools used professionally

Python

C

MATLAB

Linux

Windows

Availability

Looking for a job

Location

India

Authorized to work in

Salary expectations

70k+ INR

Job categories

Skills

RTL Design Verilog SystemVerilog RISC V ASIC Design RTL To GDSII Flow Static Timing Analysis Timing Closure Floor Planning Placements Clock Tree Synthesis Routing PPA Optimization Physical Verification CMOS VLSI

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