At Tata Consultancy Services, I designed transistor-level analog circuit layouts and used device matching, symmetry, and guard-ring techniques to support circuit performance. I reduced parasitic-induced performance degradation by 40% through post-layout extraction and simulation with Cadence Spectre, and achieved sign-off before tape-out.
As an Embedded Hardware Engineer at Cisco, I built sensor-based hardware solutions and developed Embedded C firmware. Most recently, as an Instructional Student Assistant at CSU Northridge, I supported electronic-system validation through lab testing, simulation review, and verification of experimental results.
