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Mohammad Radwan

@mohammadradwan

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I design silicon-proven analog and power-management ICs for wireless, optical, and high-speed I/O systems.

United States

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What I'm looking for

I'm looking to design and verify analog, mixed-signal, power-management, wireless, or high-speed I/O ICs, building on silicon-proven circuit design and research in equalization and optical receivers.

I've designed and verified silicon-proven power-management ICs at Vidatronic, including switched-capacitor regulators, current references, LDOs, and boost converters across 40 nm, 130 nm, and 180 nm processes.

At Intel Labs, I developed layout automation scripts using SKILL and Tcl and designed and verified a scalable, high-PSRR capacitor-less mixed-mode LDO in Intel 16.

My doctoral research at The Ohio State University focuses on high-speed I/O interfaces, including speculative decision-feedback equalizers for optical and PAM-N wireless receivers. I've also taught ECE courses while publishing research on equalization, optical receivers, and clock and data recovery.

I build on a foundation in analog IC design, RF circuit design, power management, and frequency synthesis, using Cadence Virtuoso, MATLAB, Python, Verilog-A, and VHDL.

Experience

Work history, roles, and key accomplishments

Graduate Research/Teaching Assistant

The Ohio State University

Aug 2020 - Dec 2024 (4 years 4 months)

Conducted research on novel speculative DFE structures for optical receivers and taught courses including ECE 5307, ECE 3027, and ECE 2020.

Wireline Receivers Teaching Matlab Pyxis Mentor AFS Python C++LaTeX

Graduate Intern

Intel Corporation

May 2022 - Aug 2022 (3 months)

Developed layout automation scripts using SKILL/Tcl and designed and verified a scalable, high-PSR capacitor-less mixed-mode LDO in Intel 16.

Tcl Layout Automation Mixed Mode Verification

Graduate Research/Teaching Assistant

Cairo University

Jan 2017 - Aug 2020 (3 years 7 months)

Delivered courses in analog circuits and digital logic design, and completed an MSc thesis on DC-DC converter design for NB-IoT applications.

DC DC Converters NB IoT Analog Circuits Digital Logic Design Teaching Buck Converter

Senior IC Design Engineer

Vidatronic Inc.

Apr 2019 - Jul 2020 (1 year 3 months)

Designed low-power fully-integrated LDOs as sub-blocks of a PMIC and a switched-capacitor boost converter.

PMICs Boost Converters

IC Design Engineer

Vidatronic Inc.

Dec 2016 - Apr 2019 (2 years 4 months)

Designed and verified energy-efficient power management circuits, including a switched-capacitor regulated voltage-doubler and a high-precision, low-power current reference IP.

Power Management Voltage Doubler Current References 40nm 130nm 180nm

BSc Graduation Project

Cairo University

Dec 2015 - Jul 2016 (7 months)

Designed and fabricated a low power transceiver for IoT applications and designed a low-power programmable frequency divider for sub-GHz integer PLL.

IoT Frequency Divider Fabrication

Education

Degrees, certifications, and relevant coursework

The Ohio State University

Doctor of Philosophy, Electrical and Computer Engineering

2020 - 2024

Grade: 4.0/4.0

PhD in Electrical and Computer Engineering with a research focus on high-speed I/O interfaces and novel equalizer structures. Achieved a perfect GPA of 4.0/4.0.