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Shivani Pandey

@shivanipandey2

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ECE student at VIT with ISRO-PRL experience automating Python-based data acquisition and testing.

India

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What I'm looking for

I’m seeking a Design Verification / RTL Verification Engineer role where I can apply my RTL and verification fundamentals alongside my hands-on experience.

At ISRO-PRL, I developed Python scripts for real-time data acquisition, processing, and test automation in a Linux-based environment. I also performed system validation and debugging, and documented test procedures and technical reports.

As an R&D Intern at Birla Institute of Technology, I characterized devices and validated prototypes for a dual-band wearable antenna system using CST Microwave Studio. I’m seeking a Design Verification / RTL Verification Engineer role, building on my self-study in Digital Design, Verilog HDL, SystemVerilog, and foundational UVM/TLM concepts.

Experience

Work history, roles, and key accomplishments

Summer Intern

ISRO-PRL

May 2025 - Jul 2025 (2 months)

Developed Python scripts for real-time data acquisition, processing, and test automation in a Linux-based environment. Performed system validation, debugging, and data quality analysis, and documented test procedures and technical reports.

Python Docker PostgreSQL YAML Linux API Development Data Processing Automation Systems Validation

R&D Intern

Birla Institute of Technology

Jun 2024 - Jul 2024 (1 month)

Performed device characterization, simulation-driven analysis, and hardware-software integration validation on a dual-band wearable antenna system using CST Microwave Studio. Debugged design issues and validated prototypes against measurement specifications.

CST Studio Suite Antenna Design Simulation Prototyping Technical Documentation