Looking for a job

Manar Tarek

@manartarek

Message

I build and verify Verilog RTL for FPGA and ASIC-oriented digital IC designs.

Egypt

Message

What I'm looking for

I'm seeking an opportunity to apply my RTL design, verification, and FPGA development experience to advanced ASIC and FPGA designs while continuing to grow through practical, project-based engineering work.

I'm building and verifying Verilog RTL for FPGA and ASIC-oriented digital IC designs, including a CNN inference accelerator on Xilinx Zynq.

Through NTI's Hire&Ready Digital IC Design track and internship, I've developed testbenches for functional verification and strengthened my RTL, synthesis, and simulation workflows with Xilinx Vivado and QuestaSim.

My projects include a direct-mapped cache controller with an AHB-Lite interface, an FSM-controlled SPI slave with single-port RAM, and a DSP48A1-compatible pipelined arithmetic unit. I verify designs using timing-aware and self-checking testbenches.

I'm completing a B.Sc. in Electronics and Communication Engineering and bring additional hands-on experience in embedded systems, Arduino robotics, C/C++, Python, and Git/GitHub.

Experience

Work history, roles, and key accomplishments

Digital IC Design Engineer

National Telecommunication Institute (NTI)

Jun 2025 - Aug 2025 (2 months)

Completed an intensive internship in digital IC design and verification, developing and executing testbenches for functional verification. Gained hands-on experience with Xilinx Vivado and QuestaSim for simulation and synthesis.

Verilog RTL Design Functional Verification QuestaSim Simulation Synthesis