Open to opportunities

Ahmed Eid

@ahmedeid

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Electronics Engineer with ASIC design experience

Egypt

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What I'm looking for

Seeking a challenging role in ASIC design or digital IC design

I am a highly motivated and detail-oriented electronics engineer with a strong background in ASIC design and verification. My graduation project involved designing and verifying a MIPI I3C system using ASIC, where I worked as a team leader and implemented various components such as register files and dynamic addressing engines.

I have also gained experience in internships, including working with Siemens EDA on FinFET physics and modeling for circuit simulation, and with Si-Vision on IC layout. Additionally, I have worked on embedded firmware development with El-Sewedy Electrometer and participated in the TL-Verilog mentorship program with Redwood EDA.

I have a strong foundation in digital IC design, having completed a diploma program with Eng. Ali Eltemsah, where I learned about efficient RTL coding, static timing analysis, and low power design techniques. I have also completed various online courses, including FPGA design for embedded systems, MATLAB programming, and SoC verification using SystemVerilog.

Experience

Work history, roles, and key accomplishments

Intern

Siemens EDA

Nov 2023 - Dec 2023 (1 month)

FinFET physics and modeling for circuits simulation course, reviewed semiconductor physics, quantitative analysis of MOS capacitor and long channel MOSFET

Capacitor

IC Layout Intern

Si-Vision

Nov 2023 - Nov 2023 (0 months)

IC layout internship, worked on IC fabrication process, short channel MOSFETs, and analog integrated components

Layout

Embedded Firmware Intern

El-Sewedy Electrometer

Nov 2023 - Nov 2023 (0 months)

Embedded firmware development of ATMEL SAM4 micro-controller, implemented GPIO, power manager, and SPI drivers

Firmware ATMEL SAM4 SPI MISRA Rules

Graduation Project Team Leader

Cairo University

Apr 2019 - Nov 2023 (4 years 7 months)

Team leader of graduation project, designed system architecture, implemented register file, SDA, SCL driver, dynamic addressing engine, and target reset engine

Systems Architecture Dynamic Addressing Engine

TL-Verilog Mentor

Redwood EDA

May 2023 - Jun 2023 (1 month)

TL-Verilog mentorship program, worked on microprocessor implementation using transaction-level modeling

Verilog M5 Text Processing Language

Education

Degrees, certifications, and relevant coursework

Cairo University

Bachelor, Electronics and Electrical Communications Engineering

2019 - 2024

Grade: Good 73%

Activities and societies: Team Leader for graduation project; designed system architecture, implemented Register File, SDA, SCL driver, Dynamic Addressing engine, and Target Reset engine.

Studied Electronics and Electrical Communications Engineering at the Faculty of Engineering. Focused on system architecture design and implementation for various components as part of the graduation project, which involved ASIC Design and Verification.