My DDR5 Physical Layer (PHY) Interface Design graduation project involved designing and implementing the TX Driver and On-Die Termination circuitry, with programmable drive strengths such as Tx240 and Tx120.
I developed a custom pre-driver stage for signal integrity and slew-rate control, and engineered signal-conditioning logic for transmitter configuration and impedance calibration.
During my Analog IC Design internship at ITI, I designed and biased a Folded Cascode amplifier with common-mode feedback, then designed a 2-stage amplifier using Miller Compensation for stability.
