At Government Engineering College Gandhinagar, I’ve worked on RTL-to-GDSII projects including an 8-bit ALU and a complete RISC-V microchip using Verilog HDL and the Sky130 130nm PDK. I used OpenLane and Yosys for physical design, synthesis, and timing optimization.
As a VLSI Intern at Indo German Tool Room (IGTR), Ahmedabad, I designed and simulated CMOS logic circuits, including a 6T SRAM cell, and completed manual layout and physical verification in Microwind with zero DRC violations. My projects also include synchronous FIFO design and verification, and a Linux IPC simulation of an asynchronous FIFO.
