At Advanced VLSI Laboratory, IET, DAVV, I reviewed JPEG compression literature and built a MATLAB prototype to validate fixed-point arithmetic choices. I translated that prototype into a 14-module Verilog RTL codec on Kintex-7 as the basis for hardware Trojan insertion research.
My projects include a class-based SystemVerilog verification testbench for a synchronous FIFO, where eight data integrity checks passed across four test scenarios, and a parameterizable UART transceiver verified in Vivado XSim. I work with Verilog, SystemVerilog, Vivado, and XSim, and have also trained and evaluated supervised ML models using Python, NumPy, and Pandas.

