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Chitrangi Kasliwal

@chitrangikasliwal

VLSI research intern at Advanced VLSI Laboratory, IET, DAVV who translated a MATLAB JPEG prototype into a 14-module Verilog codec.

India

Message

At Advanced VLSI Laboratory, IET, DAVV, I reviewed JPEG compression literature and built a MATLAB prototype to validate fixed-point arithmetic choices. I translated that prototype into a 14-module Verilog RTL codec on Kintex-7 as the basis for hardware Trojan insertion research.

My projects include a class-based SystemVerilog verification testbench for a synchronous FIFO, where eight data integrity checks passed across four test scenarios, and a parameterizable UART transceiver verified in Vivado XSim. I work with Verilog, SystemVerilog, Vivado, and XSim, and have also trained and evaluated supervised ML models using Python, NumPy, and Pandas.

Experience

Work history, roles, and key accomplishments

Research Intern

Advanced VLSI Laboratory, IET, DAVV

Jun 2026 - Jul 2026 (1 month)

Reviewed JPEG compression literature, built a MATLAB prototype validating fixed-point arithmetic choices, and translated it into a 14-module Verilog RTL codec on Kintex-7 as the basis for hardware Trojan insertion research.

Matlab Verilog Kintex 7 Vivado Fixed Point Arithmetic JPEG Compression Hardware Security

Trainee Intern

MoreYeahs IT Technologies Pvt. Ltd.

Dec 2025 - Dec 2025 (0 months)

Trained and evaluated supervised ML models using Python, NumPy, and Pandas, covering data preprocessing, feature engineering, and performance metrics on structured datasets.

Python NumPy Pandas Machine Learning data preprocessing Feature Engineering